1. Field of the Invention
The present invention relates to an image sensor and an image capturing apparatus.
2. Description of the Related Art
In recent image capturing apparatuses including a digital camera and digital video camera, a technique of reading out an image signal from an image sensor at high speed is required to increase the number of pixels and improve the continuous shooting speed. Therefore, when a signal read out at high speed is analog-digital (A/D)-converted for each pixel, the conversion time for each pixel data must be short. A high-performance A/D conversion circuit capable of performing highly accurate conversion in a short time is necessary.
To solve this problem, research and development are in progress for a column A/D conversion image sensor in which A/D conversion circuits which are implemented by the CMOS integrated circuit technique and can be manufactured by the same process as in a CMOS image sensor are arranged for each column of pixels of the image sensor to simultaneously A/D-convert pixel signals on one row. In the column A/D conversion image sensor, the conversion rate of the A/D conversion circuit can be lowered from a readout rate for each pixel to that for each row, thus easily speeding up the readout rate of one frame of the image sensor.
As such a column A/D conversion image sensor, Japanese Patent Laid-Open No. 05-048460 discloses a ramp A/D conversion circuit which sequentially compares a ramp signal and a pixel signal using a comparator to convert the pixel signal into a digital value corresponding to the time until inversion of the output from the comparator. Unfortunately, this ramp A/D conversion circuit requires a longer time for the output from the comparator to invert as the value of the pixel signal gets larger. For example, the (N+2)-bit A/D conversion time is about four times that in N-bit conversion.
To shorten the A/D conversion time, the following method is available. In n-bit A/D conversion, first, the amplitude of an analog signal is compared with a threshold obtained by dividing the amplitude of a full-scale analog signal by 2k (k is an integer smaller than n). A/D conversion is done by a comparison with a ramp voltage. Two ramp signals with different gradients are generated to A/D-convert a pixel signal into an (n−k)-bit digital value using a ramp signal with a large gradient if the pixel signal has an amplitude higher than the threshold, or using a ramp signal with a small gradient if the pixel signal has an amplitude equal to or lower than the threshold. The A/D conversion result has (n−k) bits on the MSB side of n-bit digital data if the pixel signal has an amplitude higher than the threshold, or it has (n−k) bits on the LSB side of n-bit digital data if the pixel signal has an amplitude equal to or lower than the threshold (for example, Japanese Patent Laid-Open No. 2010-45789).
Normally, ramp signals input to an A/D conversion circuit are commonly supplied to a comparator arranged for each pixel column. However, when a ramp signal generation circuit with a gradient which varies depending on the magnitude of a pixel signal is selected, the number of comparators connected to each ramp signal generation circuit may vary for each object. If the number of connected comparators varies, the load connected to a ramp signal line changes, so the linearity of a ramp signal which changes at high speed in a predetermined amount may degrade. As a result, the A/D conversion characteristics may vary for each column. Although this problem can be solved when a ramp signal generation circuit is arranged for each column, this arrangement is undesirable as the circuit scale increases. Also, since a switch for selecting a ramp signal to be used is required for each column, the quality of a ramp signal may degrade due to noise generated by the switch, thus adversely affecting the A/D conversion characteristics such as noise and linearity.